? Harsha Gadiraju - Recent College Graduate

I'm Passionate

I'm Talented

I'm Harsha

Intel Corporation Employee

801-560-1275

harshagadiraju@outlook.com

www.harshagadiraju.com

I am Harsha Gadiraju

I am currently working as a Design Automation Engineer in Intel Corporation, Austin.I am looking for a full time opportunity in domains of VLSI design/testing/verification/validation, EDA/physical design and Computer Architecture.

I am a masters student from University of Utah in Electrical and Computer Engineering with emphasis on VLSI Design, Embedded Systems and Computer Architecture.

I have good knowledge of Semiconductor physics, CMOS VLSI Design, Digital Design, Computer Architecture, Verilog/RTL coding, ASIC Design Flow, Simulation, Static Timing Analysis, Embedded Systems, Testing and Verification of digital circuits.

I have experience with low power and high speed CMOS VLSI Design with strong background in ASIC design using Cadence and Synopsys EDA tools.

Resume

Education

  • University of Utah

    Salt Lake City, UT

    2013 - 2015

    Master of Science in Electrical and Computer Engineering

    GPA: 3.64

  • Andhra University

    Vishakhapatnam, India

    2009 - 2013

    Bachelor of Technology in Electronics and Communication Engineering

    CGPA: 8.73

Experience

  • Design Automation Engineer

    March2016 - Present

    Design Automation Engineer

    Atom DA Team, Intel Corporation, Austin, TX.

    • Supported Synthesis flow for Atom CPU team using Synopsys Design Compiler.

    • Worked on Reliability Verification (IR drops and EM checks) using RedHawk on Atom low power designs.

    • Performed scripting tasks using Perl and Tcl.

  • Graduate Research Assistant

    August 2013 - March 2016

    Graduate Research Assistant

    Rose Lab, Department of Biology, University of Utah

    • Developed frontend and backend for simulation of acoustic communication in animals in MATLAB

    • Optimized the existing code for data analysis and improved the execution time by 90%.

    Lab Website

Course Work

  • University of Utah

    Course Website

    Through the coursework, labs and project I was able to design a processor with all the steps starting from RTL Design to Place and Route involved in the ASIC design flow use state of art CAD tools. I also learnt the following concepts:

    • Basic Transistor Theory

    • CMOS Processes

    • VLSI CAD tools from Cadence and Synopsys

    • Mask Layout methods and design rules

    • Circuit Simulation and characterization

    • Custom Datapath Design

    • Design Validation

    • Full Chip Assembly

    As a part of labs, drew layouts, wrote test benches, preformed analog simulations on standard cells, performed all the steps involved in ASIC design flow.

    Projects :

    Designed and synthesized a 16 bit 22 MIPS instruction set processor using 0.5µm CMOS technology

    Designed a custom library of standard cells

    Course Website

    Through the coursework and labs I gained insights into the advanced concepts of VLSI design, scripting, best of breed CAD tools, commercial design flows, design optimization and advanced process technologies. I also learnt the following advanced VLSI design concepts:

    • Design methodologies and IP design

    • Advanced logic circuit styles

    • Noise sources and signal integrity in digital design

    • Design techniques for dynamic and static power reduction

    • Interconnect analysis

    • Performance verification

    • Static Timing Analysis

    As a part of labs, wrote HSpice netlists, performed simulations by varying parameters of transistors.

    Projects :

    4 Stage pipelined 8 bit multiplier design.

    Course Website

    I learnt the following concepts:

    • Principles of modern high-performance computer and micro architecture

    • Pipelining

    • Control and data hazards and their prevention methods

    • Out of order processors

    • Cache structure, policies and coherence protocols

    • CPU memory systems

    • Virtual memory

    Projects :

    Performance analysis of 4 stage pipelined out of order processor

    Memory modelling of Caches

    Course Website

    I learnt various formal hardware techniques in this course. I learnt the following concepts:

    • Conventional verification techniques such as SAT solvers and BDDs

    • Equivalence Verification

    • VLSI testing

    • Fault models

    Projects :

    Equivalence verification of digital circuits by computing Groebner basis in Boolean rings using ZBDDS in C

    Course Website

    For this course we used ARM Cortex M3 and Microsemi FPGAs to learn how to design, build and program embedded systems. I learnt the following concepts:

    • Principles and practices of modern embedded systems design

    • ARM architecture and assembly

    • Memory mapped peripherals

    • Serial busses

    • Interrupts

    As part of labs, implemented FPGA hardware, made signal observations and measurements with logic analyzer and oscilloscope, understood debugging techniques for the ARM development by interfacing the hardware to GPIO’s, switches and LED’s, memory mapped programming and interfacing to buses such as APB3 and AHB and interrupt programming.

    Projects :

    Shape based security using smart fusion FPGA board

    For this course we used beagle board black board. I learnt how to write efficient robust C code for embedded systems. I also learnt the following concepts:

    • Principles of embedded software

    • Efficient C programming for embedded systems

    • Interrupts

    Projects:

    Launch interceptor module in C

    In this course, I learnt about device structure and physics of various semiconductor devices such as BJTs and MOSFETs.

    Andrha University

    • VLSI Design and Embedded Systems

    • Computer Architecture and Organization

    • Microprocessors and Applications

    • Digital Logic Design

    • Linear ICs and Applications

    • Electronic Devices and Circuits

    • Data Structures

Skills

  • Programming Languages

    I am familiar with C, C++, ARM Assembly,Verilog and Python.

    C
    11
    Verilog
    10
    Python
    9
    C++
    7
    Perl
    7
    Tcl
    5

  • CAD tools

    I am familiar with CAD tools such as Cadence Virtuoso, Synopsys DC Compiler, Synopsys IC Compiler, SoC Encounter, HSpice, Synopsys Primetime, ModelSim and RedHawk.

    Cadence Virtuoso
    20
    Synopsys DC Compiler
    20
    SoC Encounter
    10
    Synopsys IC Compiler
    10
    Synopsys Primetime
    10
    ModelSim
    15
    Hspice
    5
    RedHawk
    10

  • Embedded System tools

    I worked with the following tools while programming Embedded Systems: Altium Designer, MicroSemi libero and Soft Console IDE.

  • Operating Systems

    I am familiar withWindows, Linux and Mac operating systems.

    Windows
    70
    Linux
    20
    Mac
    10

Honors and Awards

  • Best Paper Award
    Quest 2011

  • Best Paper Award
    TRANCE 2012

Leadership

  • Student Organizer
    TRANCE 2012

  • Organizer
    SRKR ECE Day

Projects

Contact

Where I am based

Get in Touch

5701 S Mo Pac Expy, Apt 122, Austin, TX-78749
801-560-1275
harshagadiraju@outlook.com
www.harshagadiraju.com

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